One desk. One flow. — built by someone who got tired the hard way.
SiliFlow is the story of one question: why should a student need a shelf of tools from six vendors just to see a waveform? This page is about the product — and the person who finally stopped complaining and started building.
SiliFlow is a desktop IDE that walks a chip from RTL to GDS2 — with every stage verdict shown beside the code.
Chip design today is scattered: one vendor app to simulate, another to synthesize, a third to lint, a fourth to time-analyze — each with its own install ritual, its own license server and its own Tcl dialect. SiliFlow puts the whole flow in one workspace. You open a project, press run on the stage you need, and read the result right next to the line that produced it.
Simulation is live today — drop in raw-source RTL, get waveforms, click from a signal back to the source that drove it. Synthesis is next on the public roadmap; lint, CDC, RDC, DFT and STA follow one stage at a time, shaped by what designers ask for. The last stop is layout: GDS2, ready for the fab.
It is a real GUI application — buttons, panels, waveforms, not a shell prompt — running native on Windows, Linux and macOS. A compiled core keeps it fast: cold start in seconds, modest memory, no typos-waiting-while-you-type. Everything runs locally; your netlists and GDS2 never upload anywhere.
Model: free for students, hobbyists and anyone who wants to learn. Companies pay one simple license — no seat-counting rituals, no reloadable dongles.
- ✓★ 8 STAGES · ONE WORKSPACE
- ✓★ SIMULATION LIVE · WAVEVIEWER + CROSS-PROBE
- ✓★ SYNTHESIS NEXT · PUBLIC ROADMAP
- ✓★ REAL GUI · TERMINALS NOT REQUIRED
- ✓★ NATIVE · WINDOWS / LINUX / MACOS
- ✓★ STARTS IN SECONDS · STAYS OUT OF YOUR WAY
- ✓★ RAW-SOURCE RTL IN · RESULTS BESIDE THE CODE
- ✓★ FREE FOR LEARNERS · SIMPLE COMPANY LICENSE
JIGNESH GIRI — FOUNDER, SILIFLOW
- YEAR
- 3RD — B.TECH, EE (VLSI)
- BIO
- 50% STUDENT, 50% REVENGE ARC
- NEMESIS
- TOOL SETUP, ALL FORMS
- MOTTO
- JUST SHOW ME THE WAVEFORM
- COFFEE → GDS2
- COMPILING
Third year. EE — VLSI. The toolchain bit first.
Jignesh Giri did not, to be clear, set out to found an EDA company. There was no deck, no “disrupting the industry” slide, not even a plan. There was a third-year B.Tech student in Electronics (VLSI) who wanted one waveform before the semester ended — and the toolchain had other ideas.
The vendor suites wanted quotes his department couldn't sign and license servers nobody could configure. The free route, Icarus Verilog, is a great little engine with a great big catch: after downloading it you get a terminal, a wave viewer that lives in some other window, and a compile ritual you memorize like homework. An hour of setup, ten minutes of actual design, every single time.
One evening, somewhere between flag number fourteen and another mystery viewer crash, the thought arrived: someone should fix this. He waited. Nobody came. So instead of sleeping like a sensible person, he started building the fix.
SiliFlow is that fix, let out into the world: one app from RTL to GDS2, free for everyone the tools were never built for — students, hobbyists, the graduate engineer on their first block. It runs wherever he works: Windows in the lab, Linux on the cluster, and macOS when the coffee shop wifi allows.
“Even downloading Icarus couldn't get me to the code. Everything fought the design instead of running it. So I built the app I wanted to open — and now anyone can.”
▲ NOW
Simulation that just works
The beta simulates raw RTL today and streams waveforms cross-probed with your source. Try it — it is free.
▷ NEXT
Synthesis in the same window
Elaborate to netlist with timing and area reports, annotated onto the same editor you write in.
■ PLANNED
The full road to GDS2
Lint, CDC, RDC, DFT, STA and formal — and layout ready for the fab. One stage, one public vote at a time.